The present inventive concepts relate to methods for fabricating semiconductor devices.
With advances in the electronic technology, down-scaling of semiconductor devices is rapidly progressing. Accordingly, demands for highly integrated and low-power consuming semiconductor chips may be gradually increasing. In order to achieve high integration and lower power consumption of semiconductor chips, an aspect ratio of a wiring layer may be increased.
In the light of the foregoing, various studies of methods for forming via holes in a secure manner while reducing damage to a lower wiring in the wiring layer having an increased aspect ratio may be conducted.